library ieee;
use ieee.std_logic_1164.all;

entity forwarder is
  port (
    exRs, exRt, memRd, wbRd :     in std_logic_vector(4 downto 0);
    memRegWrite, wbRegWrite :     in std_logic;
    forwardA, forwardB      :     out std_logic_vector(1 downto 0)

  );
end forwarder;

architecture behavioral of forwarder is
  signal EX_Hazard_A, EX_Hazard_B, MEM_Hazard_A, MEM_Hazard_B : std_logic;

begin

   
   
--1. EX hazard from the book
  EX_Hazard_A <= '1' when (memRegWrite = '1' and not ((memRd xnor "00000") = "11111") and (memRd xnor exRs) = "11111") else
                 '0';
     --ForwardA = 10

  EX_Hazard_B <= '1' when (memRegWrite = '1' and not ((memRd xnor "00000") = "11111") and (memRd xnor exRt) = "11111") else
                 '0';
      --ForwardB = 10
      
--2. MEM hazard from the book

  MEM_Hazard_A <= '1' when (wbRegWrite = '1' and not ((wbRd xnor "00000") = "11111") and (wbRd xnor exRs) = "11111") and EX_Hazard_A = '0' else
                  '0';
    --ForwardA = 01
    
  MEM_Hazard_B <= '1' when (wbRegWrite = '1' and not ((wbRd xor "00000") = "11111") and (wbRd xnor exRt) = "11111") and EX_Hazard_B = '0' else
                  '0';
    --ForwardB = 01
     
  forwardA <= EX_Hazard_A & MEM_Hazard_A;
  forwardB <= EX_Hazard_B & MEM_Hazard_B;
  


    
end behavioral;